Algebraic Semantics of Configuration Relocation in Reconfigurable Computing

The square cells specified by Ruby language, called Ruby cells, can be relocated by either rotation, horizontal flip, vertical flip or shifting in a regular array structure such as FPGA (Field Programmable Gate Array) fabric. In this paper, our research has shown that those relocating cells can be specified and reasoned formally by algebraic laws of Ruby algebra and Group theory. As a result, applied for checking whether a given regular array structure and a given feasible schedule allow a feasible placement in FPGA. 1 An Informal Description of Relocation of A Rectilinear Configuration Configurations can be relocated by either rotation, horizontal flip, vertical flip or shifting in a regular array structure such as FPGA fabric. Relocation behaviours will be formalised by using Ruby algebra and Group theory for specification and reasoning. But before reaching the formalization the behaviours of relocation we should have a look on their following informal descriptions represented in [1]. The partially reconfigurable FPGA design is powerful but it faces limitations imposed by configuration locations determined at compile time. If two different configurations were mapped at compile time to overlapping locations in the FPGA, only one of these configurations can be present in the array at any given moment. They cannot operate simultaneously. However, if somehow the final FPGA location can be determined at runtime, one or both of these overlapping configurations can be shifted to a new location that was previously unused to allow for simultaneous use. Figure 1 illustrates a situation in which relocation can be applied. The darkly shaded mapping is already present on the FPGA. The lightly shaded mapping is a new mapping that is also to be placed on the FPGA. However, since the first and second configurations have several cell locations in common, they cannot both be present on a traditional partially reconfigurable FPGA simultaneously. However, an FPGA with relocation ability can modify the second configuration to fit the unused space on the grid, thereby allowing both mappings to be present without one overwriting the other's information. Figure 1 shows the steps taken to relocate the second configuration to available cells.